Abstract

Electrical bistability of Cu₂FeSnS₄ (CFTS) thin films fabricated via successive ionic layer adsorption and reaction (SILAR) method was studied here. The SILAR method is a simple and cost-effective method for large area thin film production. Though CFTS thin films have been fabricated for the last few years, neither the electrical memory applications nor the electrical bistability of these films has been studied yet. In this report, we have shown that the electrical characteristics of the CFTS films could be useful for the random-access memory (RAM) applications. A detailed investigation to understand the electrical bistability has been carried out. We found that conducting channels were formed inside the films when a suitable bias voltage is applied and that could be reset with an opposite bias voltage to establish electrical bistability. The p-n junction configuration restricted the percolation and formation of conducting filament. Thus, no electrical bistability were observed for the CFTS p-n junction.